Buuered Banks in Multiprocessor Systems

A memory design based on logical banks is analyzed for shared memory mul-tiprocessor systems. In this design, each physical bank is replaced by a logical bank consisting of a fast register and subbanks of slower memory. The subbanks are buuered by input and output queues which substantially reduce the eeective cycle time when the reference rate is below saturation. The principal contribution of this work is the development of a simple analytical model which leads to scaling relationships among the eeciency, the bank cycle time, the number of processors, the size of the buuers, and the granularity of the banks. These scaling relationships imply that if the interconnection network has suucient bandwidth to support eecient access using high-speed memory, then lower-speed memory can be substituted with little additional inter-connection cost. The scaling relationships are shown to hold for a full datapath vector simulation based on the Cray Y-MP architecture. The model is used to develop design criteria for a system which supports 192 independent reference streams, and the performance of this system is evaluated by simulation over a range of loading conditions.